� June 21, 2005 ISL6558
Data Sheet FN9027.12
Multi-Purpose Precision Multi-Phase PWM Features
Controller With Optional Active Voltage
Positioning � Pb-Free Plus Anneal Available (RoHS Compliant)
� Multi-Phase Power Conversion
The ISL6558 is a multi-phase PWM controller, which in
combination with the HIP6601B, HIP6602B, HIP6603B, or - 2-, 3-, or 4-Phase Operation
ISL6605 companion gate drivers form a complete solution � Optional Output Voltage Droop
for high-current, high slew-rate applications. The ISL6558 � Precision Channel-Current Balance
regulates output voltage, balances load currents and � Lossless Current Sensing
provides protective functions for two to four synchronous � Precision Reference Voltage
rectified buck converter channels.
- 0.8V � 1.5% Over -40�C - 85�C Range
A novel approach to current sensing is used to reduce - 0. 8V � 1.0% Over 0�C - 70�C Range
overall solution cost and improve efficiency. The voltage � Fast Transient Response
developed across the lower MOSFET during conduction is � Overcurrent and Overvoltage Protection
sampled and fed back to the controller. This lossless � Digital Soft-start
current-sensing approach enables the controller to maintain � Power Good Indication
phase-current balance between the power channels, provide � High Ripple Frequency (80kHz to 1.5MHz)
overcurrent protection, and permit droop compensation. � QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
Optional output voltage "droop" or active voltage positioning
is supported via the DROOP pin. Taking advantage of this No Leads-Product Outline
feature reduces the size and cost of the output capacitors - Near Chip-Scale Package Footprint; Improves PCB
required to support a load transient.
Efficiency and Thinner in Profile
In the event of an overvoltage, the controller monitors and
responds to reduce the risk of damage to load devices. Applications
Undervoltage conditions are indicated through a PGOOD
transition. Overcurrent conditions cause the converter to � Power Supply Control for Microprocessors
shutdown limiting the exposure of load devices. These � Low Output Voltage, High Current DC-DC Converters
integrated monitoring and protection features provide a safe � Voltage Regulator Modules
environment for microprocessors and other advanced low � Servers and Workstations
voltage circuits. � Memory and Accelerated Graphics Port Supplies
� Communication Processor and Personal Computer
Pinouts ISL6558 (20 LEAD 5X5 QFN)
ISL6558 (16 LEAD SOIC)
VCC 1 16 PWM4 20 19 18 17 16
PGOOD 2 15 ISEN1
15 ISEN4 14 PWM1
COMP 3 13 PWM2
DROOP 4 14 ISEN1 COMP 1 12 ISEN2
FB 5 13 PWM1 N/C 2
VSEN 6 12 PWM2
GND 8 11 ISEN2 DROOP 3
9 PWM3 FB 4
6 7 8 9 10
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright � Intersil Americas Inc. 2001-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
TEMP. PACKAGE PKG.
PART NUMBER (�C) DWG. #
ISL6558CB 0 to 70 16 Ld SOIC M16.15
ISL6558CB-T 16 Ld SOIC Tape and Reel M16.15
ISL6558CBZ 0 to 70 16 Ld SOIC M16.15
(See Note) (Pb-free)
ISL6558CBZA 0 to 70 16 Ld SOIC (Pb-free) M16.15
ISL6558CBZA-T 16 Ld SOIC Tape and Reel (Pb-free) M16.15
ISL6558CR 0 to 70 20 Ld 5x5 QFN L20.5x5
ISL6558CR-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
ISL6558CRZ 0 to 70 20 Ld 5x5 QFN (Pb-free) L20.5x5
ISL6558CRZ-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
ISL6558CRZA 0 to 70 20 Ld 5x5 QFN (Pb-free) L20.5x5
ISL6558CRZA-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
ISL6558IB -40 to 85 16 Ld SOIC M16.15
ISL6558IB-T 16 Ld SOIC Tape and Reel M16.15
ISL6558IBZ -40 to 85 16 Ld SOIC M16.15
(See Note) (Pb-free)
ISL6558IBZ-T 16 Ld SOIC Tape and Reel M16.15
(See Note) (Pb-free)
ISL6558IBZA -40 to 85 16 Ld SOIC M16.15
(See Note) (Pb-free)
ISL6558IBZA-T 16 Ld SOIC Tape and Reel M16.15
(See Note) (Pb-free)
ISL6558IR -40 to 85 20 Ld 5x5 QFN L20.5x5
ISL6558IR-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
ISL6558IRZ -40 to 85 20 Ld 5x5 QFN (Pb-free) L20.5x5
ISL6558IRZ-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
ISL6558IRZA -40 to 85 20 Ld 5x5 QFN (Pb-free) L20.5x5
ISL6558IRZA-T 20 Ld 5x5 QFN Tape and Reel L20.5x5
(See Note) (Pb-free)
ISL6558EVAL1 Evaluation Platform 1 (SOIC Package,
ISL6558CB + HIP6601BCB)
ISL6558EVAL2 Evaluation Platform 2 (QFN Package,
ISL6558CR + ISL6605CR)
NOTE: ntersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
June 21, 2005
VSEN - THREE-STATE
COMP X 0.9 OV R CLOCK AND FS/EN
FB X1.15 + LATCH SAWTOOTH PWM1
DROOP + PWM2
OV + +
SOFT- + + ISEN2
START PWM ISEN3
AND FAULT ISEN4
0.8V + +
- + PWM
CURRENT PHASE CHANNEL
CORRECTION NUMBER DETECTOR
June 21, 2005
Functional Pin Description FS/EN (Pin 7)
NOTE: Pin numbers refer to the SOIC package. Check PINOUT Connecting a resistor from this pin to ground sets the
diagrams for QFN pin numbers. internal oscillator frequency. The switching frequency, FSW,
of the converter is adjustable between 80kHz and 1.5MHz.
VCC (Pin 1) Pulling this pin to ground disables the converter and three-
Supplies all the power necessary to operate the chip. The IC states the PWM outputs.
starts to operate when the voltage on this pin exceeds the
rising POR threshold and shuts down when the voltage on GND (Pin 8)
this pin drops below the falling POR threshold. Connect this
pin to a 5V (�5%) supply. Bias and reference ground for all controller signals.
PGOOD (Pin 2) PWM1 (Pin 13), PWM2 (Pin 12), PWM3 (Pin 9),
Power good is an open drain output used to indicate the PWM4 (Pin 16)
status of the output voltage. This pin is pulled low when the
converter output voltage is either 10% below or 15% above The controller PWM drive signals are connected to the
the reference voltage. individual HIP660x driver PWM input pins. The number of
active channels is determined by the state of PWM3 and
COMP (Pin 3) PWM4. If PWM3 is tied to VCC, this indicates to the
Output of the internal error amplifier. Connect this pin to the controller that two channel operation is desired. In this case,
external feedback compensation network. PWM4 should be left open or tied to VCC. Tying PWM4 to
VCC indicates that three channel operation is desired.
DROOP (Pin 4)
Output voltage droop or active voltage positioning is ISEN1 (Pin 14), ISEN2 (Pin 11), ISEN3 (Pin 10),
provided by connecting this pin to the FB pin. An internal ISEN4 (Pin 15)
current source creates the droop across an external
feedback resistor, RFB. If no droop is desired, this pin MUST These pins are used to monitor the voltage drop across the
be left open. lower MOSFETs for current feedback, output voltage droop
and overcurrent protection. A resistor must be placed in
FB (Pin 5) series with each of these inputs and their respective PHASE
The FB pin is the inverting input of the internal error node. The resistor is sized such that the current feedback is
amplifier. Connect this pin to the external feedback 50�A at full load. Sense lines corresponding to inactive
compensation network and a resistor divider from the output channels should be left open. Inactive channels are those in
for proper control and protection of converter load. which the PWM pin has been tied to VCC or left open.
VSEN (Pin 6) Thermal Pad (in QFN only)
This pin is connected through a resistor divider to the
converter's output voltage to provide remote sensing. The In the QFN package, the pad underneath the center of the
undervoltage and overvoltage protection comparators trigger IC is a thermal substrate. The PCB "thermal land" design
off this input. for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
June 21, 2005
Typical Application - 3 Phase Converter
VOUT = 0.8V(RFB + ROS)/ROS +5V BOOT
RFB RC +5V VCC PHASE
ROS CC PWM DRIVER
FB DROOP COMP GND +12V
PWM +5V BOOT
CONTROL PVCC UGATE
ISEN4 NC VCC DRIVER
RT ISEN2 LGATE RISEN2
GND ISEN1 RISEN1
VCC DRIVER PHASE
June 21, 2005
Absolute Maximum Ratings Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V Thermal Resistance (Typical Notes 1, 2, 3) JA(�C/W) JC(�C/W)
Input, Output, or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification SOIC Package (Note 1) . . . . . . . . . . . . 70 N/A
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV QFN Package (Notes 2, 3). . . . . . . . . . 35 5
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150�C
Recommended Operating Conditions
Maximum Storage Temperature Range . . . . . . . . . . -65�C to 150�C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V �5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .-40�C to 85�C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300�C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125�C
(SOIC - Lead Tips Only)
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See
Tech Brief TB379 for details.
3. JC, "case temperature" location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VCC = 5V, TA = -40�C to 85�C. Unless Otherwise Specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY POWER
Input Supply Current VCC = 5VDC; RT = 100k �1% - 10 15 mA
POWER-ON RESET (POR)
VCC Rising Threshold 4.25 4.38 4.5 V
VCC Falling Threshold 3.75 3.88 4.00 V
Reference Voltage ISL6558CB, ISL6558CR, TA = 0�C to 70�C 0.792 0.8 0.808 V
System Accuracy ISL6558IB, ISL6558IR, TA = -40�C to 85�C
OSCILLATOR ISL6558CB, ISL6558CR, TA = 0�C to 70�C 0.788 0.8 0.812 V
ISL6558IB, ISL6558IR, TA = -40�C to 85�C
-1.0 - 1.0 %
-1.5 - 1.5 %
Channel Frequency Accuracy RT = 100k. �1% 224 280 336 kHz
Adjustment Range See Figure 3
0.08 - 1.5 MHz
Disable Voltage Maximum voltage at FS/EN to disable controller. IFS/EN = 1mA - 1.2 1.0 V
- 1.33 - VP-P
Channel Maximum Duty Cycle, by Design - 75 - %
DC Gain (GNT) RL = 10K to ground - 72 - dB
Gain-Bandwidth Product (GNT) CL = 100pF, RL = 10K to ground
Slew Rate CL = 100pF, Load = �400�A - 18 - MHz
Maximum Output Voltage RL = 10K to ground
ISEN - 5.3 - V/�s
3.6 4.1 - V
Recommended Full Scale Input Current - 50 - �A
Overcurrent Trip Level 67 - 85 �A
June 21, 2005
Electrical Specifications Operating Conditions: VCC = 5V, TA = -40�C to 85�C. Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
POWER GOOD MONITOR
Undervoltage Threshold VSEN Rising - 0.92 - VREF
Undervoltage Threshold VSEN Falling
PGOOD Low Output Voltage IPGOOD = 4mA - 0.90 - VREF
- 0.18 0.4 V
Overvoltage Threshold VSEN Rising, ISL6558CB, ISL6558CR, TA = 0�C to 70�C 1.12 1.15 1.2 VREF
Percent Overvoltage Hysteresis (GNT) VSEN Rising, ISL6558IB, ISL6558IR, TA = -40�C to 85�C
VSEN Falling after Overvoltage 1.085 1.15 1.2 VREF
- 2 - %
GBD = Guaranteed By Design
GNT = Guranteed Not Tesed
ERROR Q1 L01
CORRECTION PWM PWM1
- CIRCUIT HIP6601B
0.8V + VERROR1 IL1
+ CURRENT ISEN1 RISEN1
ITOTAL AVERAGING VOUT
+ ISEN2 RISEN2
- VERROR2 Q3 L02
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6558 VOLTAGE AND CURRENT CONTROL LOOPS CONFIGURED FOR A TWO
June 21, 2005
Operation pulse width to lower the output current contribution by
Channel 2, while doing the opposite to Channel 1.
Figure 1 shows a simplified diagram of the voltage regulation
and current control loops for a two-phase converter. Both Droop Compensation
voltage and current feedback are used to precisely regulate Microprocessors and other peripherals tend to change their
output voltage and tightly control phase currents, IL1 and IL2, load current demands often from near no-load to full load
of the two power channels. during operation. These same devices require minimal
output voltage deviation from nominal during a load step.
A high di/dt load step will cause an output voltage spike. The
Output voltage feedback is applied via the resistor amplitude of the spike is dictated by the output capacitor
combination of RFB and ROS to the inverting input of the ESR (effective series resistance) multiplied by the load step
error amplifier. This signal drives the error amplifier output magnitude and output capacitor ESL (equivalent series
high or low, depending upon the scaled output voltage in inductance) times the load step di/dt. A positive load step
relation to the reference voltage of 0.8V. The amplifier output produces a negative output voltage spike and visa versa.
voltage is distributed among the active PWM channels and The overall output voltage deviation could exceed the
summed with their individual current correction signals. The tolerance of some devices. One widely accepted solution to
resultant signal, VERROR, is fed into the PWM control this problem is output voltage "droop" or active voltage
circuitry for each channel. Within this block, the signal is positioning.
compared with a sawtooth ramp signal. The sawtooth ramp
signal applied to each channel is out-of-phase with the Droop is set relative to the output voltage tolerance
others. The resulting duty cycle signal for each channel is specifications of the load device. Most device tolerance
determined by the movement of the correction voltage, specifications straddle the nominal output voltage. At no-
VERROR, relative to the sawtooth ramp. The individual duty load, the output voltage is set to a slightly higher than
cycle signals are sent to their respective HIP660x gate nominal level, VOUT,NL. At full load, the output voltage is set
drivers from the PWM pins. The HIP660x gate drivers then to a slightly lower than nominal level, VOUT,FL. The result is
switch their upper and lower MOSFETs in accordance to this a desire to have an output voltage characteristic as shown
PWM signal. by the load line in Figure 2.
Current Loop VOUT,NL
The current control loop keeps the channel currents in VOUT,NOM
balance. During the PWM off-time of each channel, the
voltage developed across the rDS(ON) of the lower MOSFET VOUT,FL
is sampled. The current is scaled by the RISEN resistor and
provides feedback proportional to the output current of each IOUT,NL IOUT,MID IOUT,MAX
channel. The scaled output current from all active channels
are combined to create an average current reference, NOMINAL LOAD LINE DROOP LOAD LINE
ITOTAL, relative to the converter's total output current. This
signal is then subtracted from the individual channel scaled FIGURE 2. SIMPLE OUTPUT DEVICE LOAD LINE
output currents to produce a current correction signal for
each channel. The current correction signal keeps each With droop implemented and a positive load step, the
channel's output current contribution balanced relative to the resulting negative output voltage spike begins from the slightly
other active channels. Each current correction signal is then elevated level of VOUT,NL. Similarly, if the load steps from full
subtracted from the error amplifier output and fed to the load, IOUT,MAX, back to no-load, IOUT,NL, the output voltage
individual channel PWM circuits. starts from the slightly lower VOUT,FL position. These few
millivolts of offset help reduce the size and cost of output
For example, assume the voltage sampled across Q4 in capacitors required to handle a given load step.
Figure 1 is higher than that sampled across Q2. The ISEN2
current would be higher then ISEN1. When the two Droop is an optional feature of the ISL6558. It is
reference currents are averaged, they still accurately implemented by connecting the DROOP and FB pins as
represent the total output current of the converter. The shown in Figure 1. An internal current source, IDROOP,
reference current ITOTAL is then subtracted from the ISEN feeds out of the DROOP pin. The magnitude of IDROOP is
currents. This results in a positive offset for Channel 2 and a controlled by the scaled representation of the total output
negative offset for Channel 1. These offsets are subtracted current created from the individual ISEN currents. IDROOP
from the error amplifier signal and perform phase balance creates a voltage drop across RFB and offsets the output
correction. The VERROR2 signal is reduced, while VERROR1
would be increased. The PWM circuit would then reduce the
June 21, 2005
voltage feedback seen at the FB pin, effectively creating the ATX supplies control the rise times of the individual voltage
output voltage droop desired as a function of load current. outputs and insure proper sequencing.
SELECTING RFB AND ROS Soft-Start Interval
If output droop compensation is not required the DROOP pin Before a soft-start cycle is initiated, the controller holds the
active channel PWM drive signals in three-state as long as
must be left open. Simply select a value for RFB and the FS/EN pin is held at ground or the voltage applied to
calculate ROS based on the following equation: VCC remains below the POR rising threshold.
ROS = RFBxV-----O----U---0-T--.--8-�--V---0---.--8---V--- (EQ. 1)
In applications where droop compensation is desired, tie the Once VCC rises above the POR rising threshold and the
FS/EN pin is released from ground, a soft-start interval is
DROOP and FB pins together. Select RFB first given the initiated. PWM operation begins and the resulting slow
following equation, where VDROOP is the desired amount of ramp-up of output voltage avoids hitting an overcurrent trip
output voltage droop at full load. This equation is contingent by slowly charging the discharged output capacitors. The
soft-start interval ends when the PGOOD signal transitions
upon the correct selection of the ISEN resistors discussed in to indicate the output voltage is within specification.
the Fault Protection section.
RFB = -V----D-5---0R----�O----A-O----P-- = 20�103xVDROOP (EQ. 2) The soft-start interval is digitally controlled by the selection
of switching frequency. The maximum soft-start interval,
Calculate ROS based on RFB using the following equation. SSInterval, can be estimated for a given application:
Where VOUT,NL is the desired output voltage under no-load
conditions. SSInterval = 2----0---4---8-- (EQ. 4)
ROS = RFBxV-----O----U----T---0-,--N-.-8--L--V---�----0----.-8----V--- (EQ. 3) where FSW is the channel switching frequency.
Initialization The converter used to create the waveforms in Figure 3 has
a switching frequency of 125kHz. The soft-start interval
Many functions are initiated by a rising supply voltage calculated for this converter is just over 16ms. From the
applied to the VCC pin of the ISL6558. Until the supply waveforms, the actual soft-start interval is just under 16ms.
voltage reaches the Power-On Reset (POR) VCC rising
threshold, the PWM drive signals are held in three-state. VCC, 2V/DIV
This results in no gate drive generation by the HIP660x gate
drivers to the output MOSFETs. Once the supply voltage POR RISING THRESHOLD VOUT, 0.5V/DIV
exceeds the POR rising threshold, the soft-start interval is
initiated. If the supply voltage drops below the POR falling 0V
threshold, POR shutdown is triggered and the PWM outputs
are again driven to three-state.
The FS/EN pin can also be used to initialize the converter. 0V
Holding this pin to ground overrides the onset of soft-start. PGOOD, 2V/DIV
Once this pin is released, soft-start is initialized and the
converter output will begin to ramp. If FS/EN is grounded 0V
during operation, a POR shutdown is triggered and the PWM
outputs are three-stated. Toggling this pin after an overvoltage FB, 0.5V/DIV
event will not reset the controller; VCC must be cycled.
Sequencing of the input supplies is recommended. An 2ms/DIV
overcurrent spike due to supply voltage sequencing could
occur if the controller becomes active before the drivers. If FIGURE 3. SOFT-START WAVEFORMS
the POR rising threshold of the controller is met before that
of the drivers, then a soft-start interval is started and could PWM Drive Signals
be completed before the drivers are active. Once the drivers
become active the controller will be demanding maximum The ISL6558 provides PWM channel drive signals for control
duty cycle due to the lack of output voltage and could cause of 2-, 3-, or 4-phase converters. The PWM signals drive the
an overcurrent trip. A soft-start interval would be initiated associated HIP660x gate drivers for each power channel.
shortly after this event and normal PWM operation would The number of active channels is determined by the status
result. The supply voltages should be sequenced such that of PWM3 and PWM4. If PWM3 is tied to VCC, then the
the controller and gate drivers are initialized simultaneously controller will interpret this as two channel operation and
or the drivers become active just before the controller. Most only PWM1 and PWM2 will be active. Since PWM4 is not
active under these conditions, simply tie it to VCC or leave it
open. If only PWM4 is tied to VCC, then the remaining three
channels are all considered active by the controller.
June 21, 2005
PWM1, 5V/DIV ISL6558 ISEN1
+ + ISEN2
0V + ITOTAL
PWM2, 5V/DIV OC ITRIP
n + ISEN3
0V 82.5�A ISEN4
0V n = ACTIVE CHANNELS
FIGURE 6. INTERNAL OVERCURRENT DETECTION
FIGURE 4. FOUR ACTIVE CHANNEL PWM DRIVE SIGNALS
The PWM drive signals are switched out of phase. The PWM VOUT (1V/DIV)
drive signal phase relationship is 360� divided by the number
of active channels. Figure shows the PWM drive signals for 0V
a four channel converter running at 125kHz. Each PWM SHORT APPLIED
drive signal is 90� out of phase with the other.
Frequency Setting IOUT (5A/DIV)
A resistor, RT, connected between the FS/EN pin and 0A
ground sets the frequency of the internal oscillator. Tying the
FS/EN pin to ground disables the oscillator, thus shutting SHORT REMOVED
down the converter. The resistor can be calculated given the
desired channel switching frequency, FSW.
10.9 � 1.1 log FSW (EQ. 5) PGOOD (5V/DIV)
RT = 10 0V
Figure 5 provides a graph of oscillator frequency vs RT. The FIGURE 7. OVERCURRENT OPERATION
maximum recommended channel frequency is 1.5MHz.
1,000 Reference Voltage
An internal 0.8V reference is used for both PWM duty cycle
500 determination as well as output voltage protection. The
reference is trimmed such that the system, including
200 amplifier offset voltages, is accurate to �1% over
100 temperature range.
50 Fault Protection
RT - kW
20 The ISL6558 protects the load device from damaging stress
10 levels. The overcurrent trip point is integral in preventing
output shorts of varying degrees from causing current spikes
5 which would damage a load device. The output voltage
detection features insure a safe window of operation for the
2 load device.
1 50 100 200 500 1,000 2,000 Overcurrent
10 20 The RISEN resistor scales the voltage sampled across the
lower MOSFET and provides current feedback proportional
CHANNEL OSCILLATOR FREQUENCY, FSW, [kHz] to the output current of each active channel. The ISEN
currents from all the active channels are averaged together
FIGURE 5. OSCILLATOR FREQUENCY vs RT to form a scaled version of the total output current, ITOTAL.
June 21, 2005
See Figure 6. ITOTAL is compared with an internally The new overcurrent trip ratio is then used to calculate the
generated overcurrent trip current, ITRIP. The overcurrent ISEN resistors for the new full load reference current.
trip current source is trimmed to 82.5�A. If ITOTAL exceeds
the ITRIP level, then the controller forces all PWM outputs RISEN = I--F-----L- x r---D----S-----(8--O--2---.-N-5---�)---x-A--K----O------C-- (EQ. 8)
into three-state. This condition results in the HIP660x gate n
drivers removing drive to the MOSFETs. The VSEN voltage One commonly over looked component which will change
due to the new overcurrent trip ratio is the feedback resistor,
will begin to fall and once it descends below the PGOOD falling RFB.
threshold, the PGOOD signal transitions low.
A delay time, equal to the soft-start interval, is entered to RFB = V-----D-----R----O------O-----P----x----K----O-----C--- (EQ. 9)
allow the disturbance to clear. After the delay time, the 82.5 � A
controller then initiates a second soft-start interval. If the
output voltage comes up and regulation is achieved, Temperature effects of the MOSFET rDS(ON) must be
reviewed when changing the overcurrent trip level.
PGOOD transitions high. If the OC trip current is exceeded
during the soft start interval, the controller will again shut Output Voltage Monitoring
down PWM operation and three-state the drivers. The
PGOOD signal will remain low and the soft-start interval will The output voltage must be tied to the VSEN pin to provide
be allowed to expire. Another soft-start interval will be feedback used to create a window of operation. If the output
initiated after the delay interval. If an overcurrent trip occurs voltage is not the reference voltage of 0.8V, it must be
again, this same cycle repeats until the fault is removed. The scaled externally down to this level. The VSEN voltage is
OC function is shown in Figure 7 for a hard short of the then compared with two set voltage levels which indicate an
output which is applied for only a brief moment. The overvoltage or undervoltage condition of the output.
converter quickly detects the short and attempts to restart Violating either of these conditions results in the PGOOD pin
twice before the short is removed. output toggling low to indicate a problem with the output
Overcurrent protection reduces the regulator RMS output
current under worst case conditions to 95% of the full load OVERVOLTAGE
The VSEN voltage is compared with an internal overvoltage
SELECTING RISEN protection (OVP) reference set to 115% of the internal
reference. If the VSEN voltage exceeds the OVP reference,
The procedure for determining the value of RISEN is to the comparator simultaneously sets the OV latch and
insure that it scales a channel's maximum output current to triggers the PWM output low. The drivers turn on the lower
50�A. This will insure that the overcurrent trip point is MOSFETs, shunting the converter output to ground. Once
properly detected when a current limit of 165% of the the output voltage falls below the nominal output voltage, the
converter's full load current is breached. The ISEN resistor PWM outputs are placed in three-state. This prevents
can be calculated as follows: dumping of the output capacitors back through the lower
MOSFETs. If the overvoltage conditions persist, the PWM
RISEN = I--F-----L- x r---D----S-----(--O------N----)- (EQ. 6) outputs are cycled between the two states similar to a
n 50�A hysteretic regulator. The OV latch can only be reset by
cycling the VCC supply voltage to initiate a POR and begin a
where IFL is the maximum output current demanded by the soft-start interval.
load device and `n' is the number of active channels.
OC TRIP LEVEL ADJUSTMENT
The VSEN voltage is also compared to a undervoltage (UV)
Setting the full load reference current, ITOTAL, to 50�A is reference which is set to 90% of the internal reference. If the
recommended for most applications. The ratio between the VSEN voltage is below the UV reference, the power good
desired full load reference current and the internally set monitor triggers PGOOD to go low. The UV comparator does
overcurrent trip current is the overcurrent trip ratio, KOC. For not influence converter operation.
those applications where an OC trip level of 1.65 times
ITOTAL is insufficient, the full load reference current can be VSEN SCALING
scaled differently. Care must be taken in selection of certain
components once the desired OC trip ratio is determined. The output voltage, VOUT, must be fed back to the VSEN pin
separately from the feedback components to the FB pin. If
KOC = --8---2----.-5----�----A---- (EQ. 7) VSEN and FB are tied together, the error amplifier will hold
ITOTAL the VSEN voltage at the reference level while the actual
output voltage level could be much different. This would
mask the output voltage and prevent the protection features
June 21, 2005
from reacting to undervoltage or overvoltage conditions at There are two sets of critical components in a DC-DC
the proper time. converter using a ISL6558 controller and HIP660x gate
drivers. The switching components are the most critical
If the output voltage is not the same as the internal 0.8V because they switch large amounts of energy, and therefore
reference, then a resistor divider scaled like the FB resistors tend to generate equally large amounts of noise. Next are
is required as shown is Figure 8. Otherwise, the output the small signal components which connect to sensitive
voltage should be tied directly back to the VSEN pin without nodes or supply critical bypassing current and signal
a resistor divider. coupling.
VOUT RFB A multi-layer printed circuit board is recommended. Figure 9
shows the connections of the critical components for one
ROS FB output channel of the converter. Note that capacitors CIN
DROOP and COUT could each represent numerous physical
RFB VSEN capacitors. Dedicate one solid layer, usually the middle layer
of the PC board, for a ground plane and make all critical
ROS ISL6558 component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
FIGURE 8. VSEN RESISTOR DIVIDER CONFIGURATION plane into smaller islands of common voltage levels. Keep
the metal runs from the PHASE terminal to the output
PGOOD SIGNAL inductor short. The power plane should support the input
power and output power nodes. Use copper filled polygons
The undervoltage comparator and overvoltage latch feed on the top and bottom circuit layers for the phase nodes.
into the power good monitor and are NOR'd together. If Use the remaining printed circuit layers for small signal
either indicates a fault, the power good monitor triggers the wiring. The wiring traces from the HIP660x driver to the
PGOOD output low. A high on this open drain pin indicates power MOSFET gates and source should be sized to carry
proper output voltage. at least 1A of current.
Application Guidelines The switching components and HIP660x gate drivers should
be placed first. Locate the input capacitors close to the
Layout Considerations power switches. Minimize the length of the connections
Layout is very important in high frequency switching between the input capacitors, CIN, and the power switches.
converter design. With MOSFETs switching efficiently at Position both the ceramic and bulk input capacitors as close
greater than 100kHz, the resulting current transitions from to the upper MOSFET drain as possible. Locate the output
one device to another cause voltage spikes across the inductors and output capacitors between the MOSFETs and
interconnecting impedances and parasitic circuit elements. the load. Place the HIP660x gate drivers close to their
These voltage spikes can degrade efficiency, radiate noise respective channel MOSFETs.
into the circuit, and lead to device overvoltage stress.
Careful component layout and printed circuit design The critical small signal components include the bypass
minimizes the voltage spikes in the converter. capacitors for VCC on the ISL6558 controller as well as
those on VCC and PVCC of the HIP660x gate drivers.
As an example, consider the turnoff transition of the PWM Position the bypass capacitors, CBP , close to the device
upper MOSFET. Prior to turnoff, the upper MOSFET was pins. It is especially important to place the feedback
carrying the channel current. During turnoff, current stops resistors, RFB and ROS, and compensation components, RC
flowing in the upper MOSFET and is picked up by the lower and CC, associated with the input to the error amplifier close
MOSFET. Any inductance in the switched current path to the FB and COMP pins. Care should be taken in routing
generates a large voltage spike during the switching interval. the current sense lines such that the ISEN resistors are
Careful component selection, tight layout of the critical close to their respective pins on the controller. Resistor RT,
components, and short, wide circuit traces minimize the which sets the oscillator frequency, should be positioned
magnitude of voltage spikes. near the FS/EN pin.
June 21, 2005
+5VIN +12V USE INDIVIDUAL METAL RUNS
FOR EACH CHANNEL TO HELP
CBP VCC PVCC ISOLATE OUTPUT STAGES
ROS CBOOT CIN
COMP FS/EN COUT
ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE
FIGURE 9. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Component Selection Guidelines ESL is not a specified parameter. Work with your capacitor
supplier and measure the capacitor's impedance with
OUTPUT CAPACITOR SELECTION frequency to select a suitable component. In most cases,
multiple electrolytic capacitors of small case size perform
Output capacitors are required to filter the output inductor better than a single large case capacitor.
current ripple and supply the load transient current. The
filtering requirements are a function of the channel switching OUTPUT INDUCTOR SELECTION
frequency and the output ripple current. The load transient
requirements are a function of the slew rate (di/dt) and the The output inductor is selected to meet the voltage ripple
magnitude of the transient load current. These requirements requirements and minimize the converter response time to a
are generally met with a mix of capacitors and careful layout. load transient. In a multi-phase converter topology, the ripple
current of one active channel partially cancels with the other
Some modern microprocessors can produce transient load active channels to reduce the overall ripple current. The
rates above 200A/�s. High frequency capacitors are used to reduction in total output ripple current results in a lower
supply the initial transient current and slow the rate-of-change overall output voltage ripple.
seen by the bulk capacitors. Bulk filter capacitor values are
generally determined by the ESR and voltage rating The inductor selected for the power channels determines the
requirements rather than actual capacitance requirements. channel ripple current. Increasing the value of inductance
reduces the total output ripple current and total output
High frequency decoupling capacitors should be placed as voltage ripple. However, increasing the inductance value will
close to the power pins of the load as physically possible. Be slow the converter response time to a load transient.
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance One of the parameters limiting the converter's response time
components. Consult with the manufacturer of the load to a load transient is the time required to slew the inductor
device for any specific decoupling requirements. current from its initial current level to the transient current
level. During this interval, the difference between the two
Specialized low-ESR capacitors intended for switching levels must be supplied by the output capacitance.
regulator applications are recommended for the bulk Minimizing the response time can minimize the output
capacitors. The bulk capacitor's ESR determines the output capacitance required.
ripple voltage and the initial voltage drop following a high
slew-rate transient edge. Aluminum electrolytic capacitor ESR The channel ripple current is approximated by the following
values are related to case size with lower ESR available in
larger case sizes. However, the ESL of these capacitors equation:
increases with case size and can reduce the usefulness of the
capacitor to high slew-rate transient loading. Unfortunately, DI C H = V-----I--N------�----V----O------U----T-- x V-----O-----U-----T-- (EQ. 10)
June 21, 2005
The total output ripple current can be determined from the value found and the result is the RMS input current which
must be supported by the input capacitors.
curves in Figure 10. They provide the total ripple current as a
function of duty cycle and number of active channels,
normalized to the parameter KNORM at zero duty cycle. 0.5
KNORM = --V----O------U----T---- (EQ. 11) SINGLE
CURRENT MULTIPLIER, KCM 0.4 CHANNEL
where L is the channel inductor value. 0.3
SINGLE 3 CHANNEL
0.1 4 CHANNEL
0.6 2 CHANNEL 0
0.4 0 0.1 0.2 0.3 0.4 0.5
DUTY CYCLE (VO/VIN)
4 CHANNEL FIGURE 11. CURRENT MULTIPLIER vs DUTY CYCLE
0 MOSFET SELECTION AND CONSIDERATIONS
0 0.1 0.2 0.3 0.4 0.5 The ISL6558 requires two N-Channel power MOSFETs per
active channel or more if parallel MOSFETs are employed.
DUTY CYCLE (VO/VIN) These MOSFETs should be selected based upon rDS(ON),
total gate charge, and thermal management requirements.
FIGURE 10. RIPPLE CURRENT vs DUTY CYCLE
Find the intersection of the active channel curve and duty In high-current PWM applications, the MOSFET power
cycle for your particular application. The resulting ripple dissipation, package selection and heatsink are the
current multiplier from the y-axis is then multiplied by the dominant design factors. The power dissipation includes two
normalization factor, KNORM, to determine the total output loss components; conduction loss and switching loss. These
ripple current for the given application. losses are distributed between the upper and lower
MOSFETs according to duty cycle of the converter (see the
DITOTAL = KNORMxKCM (EQ. 12) equations below). The conduction losses are the main
component of power dissipation for the lower MOSFETs, Q2
INPUT CAPACITOR SELECTION and Q4 of Figure 1. Only the upper MOSFETs, Q1 and Q3
have significant switching losses, since the lower device turn
Use a mix of input bypass capacitors to control the voltage on and off into near zero voltage.
overshoot across the MOSFETs. Use ceramic capacitors for
the high frequency decoupling and bulk capacitors to supply The following equations assume linear voltage-current
the RMS current. Small ceramic capacitors can be placed
very close to the upper MOSFET to suppress the voltage transitions and do not model power loss due to the reverse-
induced in the parasitic circuit impedances.
recovery of the lower MOSFETs body diode. The gate-
Two important parameters to consider when selecting the
bulk input capacitor are the voltage rating and the RMS charge losses are dissipated in the HIP660x drivers and
current rating. For reliable operation, select a bulk capacitor
with voltage and current ratings above the maximum input don't heat the MOSFETs. However, large gate-charge
voltage and largest RMS current required by the circuit. The
capacitor voltage rating should be at least 1.25 times greater increases the switching time, tSW which increases the upper
than the maximum input voltage and a voltage rating of 1.5 MOSFET switching losses. Ensure that both MOSFETs are
times is a conservative guideline. The RMS current
requirement for a converter design can be approximated with within their maximum junction temperature at high ambient
the aid of Figure 11. Follow the curve for the number of active
channels in the converter design. Next determine the duty temperature by calculating the temperature rise according to
cycle for the converter and find the intersection of this value
and the active channel curve. Find the corresponding y-axis package thermal-resistance specifications. A separate
value, which is the current multiplier. Multiply the total full load
output current, not the channel value, by the current multiplier heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
PUPPER = I--O-----2----�-----r--D----S----(--O-----N----)---�-----V----O-----U----T-- + -I-O------�-----V----I--N-----�-----t--S----W------�-----F----S----W---
PLOWER = I--O-----2----�-----r--D----S----(--O-----N----)---�-----(---V----I--N-----�----V-----O----U----T----) (EQ. 14)
June 21, 2005
Quad Flat No-Lead Plastic Package (QFN) L20.5x5
Micro Lead Frame Plastic Package (MLFP)
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL MIN NOMINAL MAX NOTES
A1 0.80 0.90 1.00 -
A3 - 0.02 0.05 9
D - 0.65 1.00 5, 8
D2 0.20 REF 9
E1 0.23 0.30 0.38 7, 8
e 5.00 BSC 9
L 4.75 BSC 7, 8
2.95 3.10 3.25 -
5.00 BSC 2
2.95 3.10 3.25
0.20 - -
0.35 0.60 0.75
Nd 5 3
Ne 5 3
P - - 0.60 9
- - 12 9
Rev. 4 11/04
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
10. Compliant to JEDEC MO-220VHHC Issue I except for the "b"
June 21, 2005
Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N INCHES MILLIMETERS
INDEX H 0.25(0.010) M B M SYMBOL MIN MAX MIN MAX NOTES
-B- A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
123 B 0.014 0.019 0.35 0.49 9
D L C 0.007 0.010 0.19 0.25 -
h x 45o
SEATING PLANE D 0.386 0.394 9.80 10.00 3
E 0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
-C- H 0.228 0.244 5.80 6.20 -
� h 0.010 0.020 0.25 0.50 5
e A1 L 0.016 0.050 0.40 1.27 6
B 0.10(0.004) N 16 16 7
0.25(0.010) M C A M B S 0o 8o 0o 8o -
Rev. 1 02/02
1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
June 21, 2005
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