IR 3/16 Encode/Decode IC
HSDL-7001-2500 pc, tape
Features Description Schematic SIR IR_TXD
� Compliant with IrDA 1.0 The HSDL-7001 modulates and TXD
Physical Layer Specs demodulates electrical pulses SIR IR_RCV
from Hewlett-Packard's RCD DECODE
� Interfaces with IrDA 1.0 HSDL-1001 Infrared transceiver
Compliant IR Transceivers module and other IrDA-compliant /NRST INT_CLOCK
transceivers. The HSDL-7001 can A0
� Used in Conjunction with be used with a microcontroller/ A1 CLOCK
Standard 16550 UART microprocessor that has a serial A2 DIVIDE
communication interface (UART).
� Transmits/Receives either Prior to communication, the 16XCLK 16 VCC
1.63 �s or 3/16 Pulse Mode processor selects the transmis- 15 OSCIN
sion baud rate. Serial data is then PULSEMOD 14 OSCOUT
� Internal or External Clock transmitted or received at the CLK_SEL 13 POWERDN
Modes prescribed data rate. 12 PULSEMOD
Pin Out 11 IR_TXD
� Programmable Baud Rate The HSDL-7001 consists of two 10 IR_RCV
state machines � the SIR (Serial 1 9 NRST
� 2.7-5.5 V Operation InfraRed) Encode and SIR Decode 16XCLK
blocks. It also contains a
� 16 Pin SOIC Package sequential block Clock Divide 2
which synthesizes the required TXD
Applications internal signal.
� Interfaces with IR The HSDL-7001 can be placed RCV
Transceivers in: into the Internal Clock Mode or
- Computer Applications: External Clock Mode. An external 4
Notebook Computers crystal is needed for the Internal A0
Sub-notebooks Clock Mode. In applications
Desktop PCs where the external 16XCLK 5
PDAs signal is provided, a crystal is not A1
Dongle or other RS-232 6
adapter There are two data transmission A2
- Telecom Applications: modes. Data can be transmitted
Modems and received in either a standard 7
Fax Machines 3/16 modulation mode or a CLK_SEL
Pagers 1.63 �s pulse mode.
- Handheld Data Collection: GND
I/O Pinout List
Pin Name Type Function
1 16XCLK DIGIN Positive edge triggered input clock that is set to 16 times the data
(SIXTNCK) transmission baud rate. The encode and decode schemes require this
signal. The signal is usually tied to a UART's BAUDOUT signal. The
16XCLK may be provided by application circuitry if BAUDOUT is not
available. This signal is required when the internal clock is not used.
2 /TXD DIGIN Negative edge triggered input signal that is normally tied to the SOUT
signal of the UART (serial data to be transmitted). Data is modulated
and output as IR_TXD.
3 RCV DIGOUT Output signal normally tied to SIN signal of a UART (received serial
data). RCV is the demodulated output of IR_RVC.
4 A0 DIGIN Clock Multiplex Signal
5 A1 DIGIN Clock Multiplex Signal
6 A2 DIGIN Clock Multiplex Signal
7 CLK_SEL DIGIN Used to activate either the Internal or External Clock. A high on this
line activates the External clock (16XCLK) and a low activates the
Internal clock. When the External clock is activated, the internal
oscillator is put in POWERDOWN MODE.
8 GND Chip Ground
9 /NRST DIGIN Active low signal used to reset the IrDA-SIR DECODE state machine.
This signal can be tied to POR (Power On Reset) or VCC. This signal can
also be used to disable any data reception.
10 /IR_RCV DIGIN Input from SIR optoelectronics. Input signal is a 3/16th or 1.6 �s pulse
which is demodulated to generate RCV output signal.
11 IR_TXD DIGOUT This is the modulated TXD signal.
12 PULSEMOD DIGIN A high level on this input puts the chip into the monoshot transmit
(with mode. In this mode, when there is a negative transition on the TXD
pulldown) input, a rising edge on the internal transmit modulation state machine
will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a
3.6864 MHz crystal, this corresponds to 1.63 �s. This mode cannot be
used in conjunction with the 16XCLK clock. It is meant to be used with
the external crystal clock. By default, this input pin is pulled to GND.
13 POWERDN DIGIN A high on this input puts only the internal oscillator cell (OSCII) in
(with POWERDOWN MODE. The cell is normally not powered down.
14 OSCOUT ANAOUT Oscillator Output
15 OSCIN ANAIN Oscillator Input
16 VCC Power
Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted
high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted
Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps) A2 A1 A0 Crystal Freq. Division
115200 0 0 0 Divided by 2
57600 0 0 1 Divided by 4
19200 0 1 0 Divided by 12
9600 0 1 1 Divided by 24
38400 1 0 0 Divided by 6
4800 1 0 1 Divided by 48
2400 1 1 0 Divided by 96
TEST PURPOSE 1 1 1 No division
1. DIMENSIONS A AND B ARE DATUMS
AND T IS A DATUM SURFACE.
�B� P 0.25 (0.010) M B M 2. DIMENSIONING AND TOLERANCING PER
16 1 8 8 PL. ANSI Y14.5M, 1982.
1 3. CONTROLLING DIMENSION: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
G DIM. MIN. MAX. MIN. MAX.
R X 45� A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
J C 1.35 1.75 0.054 0.068
�T� SEATING D 0.35 0.49 0.014 0.019
PLANE F 0.40 1.25 0.016 0.049
16 PL. M G 1.27 BSC 0.060 BSC
0.25 (0.010) M T B S A S J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0� 7� 0� 7�
PR 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
Encoding Scheme 16 CYCLES 16 CYCLES 16 CYCLES
IRTXD 7 CS
The encoding scheme relies on a pulse is delayed for 7 clock cycles For consecutive spaces, pulses
clock being present, which is set of the 16XCLK before the pulse is with a 1 bit time delay are gener-
to 16 times the data transmission set high for 3 clock cycles (or ated in series. If a logic 1 (mark)
baud rate (16XCLX). The encoder 3/16th of a bit time) and then is sent then the encoder does not
sends a pulse for every space or subsequently pulled low. This generate a pulse.
"0" that is sent on the TXD line. generates a 3/16th bit time pulse
On a high to low transition of the centered around the bit of
TXD line, the generation of the information ("0") that is being
16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLES
IRRXD 3 CS
The IrDA-SIR (Serial InfraRed) arrival of a pulse. This pulse Note 1: The stretched pulse must
decoding modulation method can needs to be stretched to be at least 3/4 of a bit time in
be thought of as a pulse stretch- accommodate 1 bit time (or 16 duration to be correctly inter-
ing scheme. 16XCLK cycles). Every pulse that preted by a UART.
is received is translated into a "0"
Every high to low transition of or space on the RXD line equal to Note 2: It is recommended that
the IR_RXD line signifies the 1 bit time. TXD remains high when not
transmitting. This ensures the
LED is off and will not interfere
with signal reception.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
INT CLK 6 CRYSTAL CYCLES
The figure above illustrates the With a 3.6864 MHz clock, this
operation of the monoshot when corresponds to a pulse of 1.63 �s.
the internal clock is set to divide The duration of this pulse is
by 2 mode, i.e., when A2=0, independent of the code A2,
A1=0, and A0=0. A rising edge A1,A0 and is always 6 clock
on the internal modulation state cycles of the crystal, corre-
machine (IRTXD OUTPUT), will sponding to the monoshot
cause the output on the IRTXD to operation.
go up for 6 crystal clock cycles.
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Storage Temperature TS -65 +150 �C
Operating Temperature TA -40 +85 �C
Output Current IO -100 100 mA
Power Dissipation 0.46 W
Input/Output Voltage PMAX -0.5 VCC + 0.5 V
Power Supply Voltage VI/VO -0.5 V
Electrostatic Protection VCC 7.0 V
1. Maximum power dissipation is given for Rth = 140 C/W (SO 16 Plastic).
2. All pins are protected from damage to static discharge by internal diode clamps to
VCC and GND.
(VCC = 2.7 to 5.5 V, TA = -20 to +85�C)
Parameter Symbol Min. Typ. Max. Units Conditions
Propagation Delay Time tpd 3.7 7.25 11.6 ns VCC = 5.5 V, CL = 50 pF
10 16 24 VCC = 2.7 V, CL = 50 pF
Output Rise Time trise 4.4 8.35 11.2 ns VCC = 5.5 V, CL = 50 pF
11 16 26 VCC = 2.7 V, CL = 50 pF
Output Fall Time tfall 50 pF
Output Capacitance on Output COUT
Pads Used for Simulation
1. Propagation Delay Time in the output buffer is the time taken from the input passing VCC/2 to the time of the output reaching
VCC/2 with 50 pF as the output load.
2. The Output Rise Time is the time taken for the outputs (RCV, IR_TXD) to rise from 10% of the original value to 90% of the final
3. The Output Fall Time is the time taken for the outputs (RCV, IR_TXD) to fall from 90% of the original value to 10% of the final
Recommended Operating Conditions
(VCC = 2.7 to 5.5 V, TA = -20 to +85�C)
Parameter Symbol Min. Typ. Max. Units Conditions
2.7 5 5.5 V
Supply Voltage VCC 0.0 VCC V VCC = 2.7 V
-20 0.44 +85 �C ioh = 2 mA
Input Voltage VI 0.7 VCC 0.11 VCC V VCC = 2.7 V
0 11 V iol = 2 mA
Ambient Temperature TA 2.2 5.4 0.3 VCC V VCC = 5.5 V
80 ioh = 2 mA
High Level Input Voltage VIH 4.5 40 0.5 V VCC = 5.5 V
iol = 2 mA
Low Level Input Voltage VIL 1630 2 0.5 V VCC = 5.5 V
1630 2 VCC = 2.7 V
Output High Voltage VOH 0.61 V VCC = 5.5 V
1710 0.15 VCC = 2.7 V
Output Low Voltage VOL 16.5 mW VCC = 5.5 V
8.1 mW VCC = 2.7 V
Output High Voltage VOH 110 mW VCC = 5.5 V
54 mW VCC = 2.7 V
Output Low Voltage VOL �A
Static Power Dissipation PSTAT 3 mA
Dynamic Power Dissipation PDYN MHz
Static Current Consumption ISTAT ns
Dynamic Current Consumption IDYN
Max Clk Frequency (16XCLK) f16XCLK 114 152 256 K
Minimum Pulse Width (IR_TXD) tmpw
Pulse Width on Monoshot tmpw 0.7 0.8 0.9 V VCC = 2.7 V
(IR_TXD and IR_RCV) 1.9 1.95 2.00 VCC = 5.5 V
Value of Pulldown Resistor Used on RDWN
POWERDOWN & PULSEMOD Input Pins 1.7 1.85 1.9 V VCC = 2.7 V
VIL_TRIG 3.25 3.4 3.60 VCC = 5.5 V
Trigger Low Level Input Voltage
(For /NRST Input Pin) VIH_TRIG
Trigger High Level Input Voltage
(For /NRST Input Pin)
1. IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7001's internal state
machine. Under normal circumstances, the clock input should not exceed 16* 115.2 Kbps or 1.8432 MHz. This product can
operate at higher clock rates, but the above is the recommended rate.
2. The Minimum Pulse Width (tmpw) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As
per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3*(1/1.8432 MHz) or 1.63 �s.
Application Circuits HSDL-7001 UART 16550
HSDL-7001 Connection to UART
TXD IR_TXD TXD SOUT
RCV IR_RCV RCV SIN
HSDL-7001 Connected to Microcontroller
HSDL-1001 HSDL-7001 MICROCONTROLLER
TXD IR_TXD TXD SDO
RCV IR_RCV A0 I01
15 pF PULSEMOD I05
F = 3.6864 MHz
OSCIN POWERDN I06
15 pF OSCOUT
NRST 10 k
NOTE: POWERDN CAN BE USED AS A BASIC CHIP SELECT.
THE HSDL-7001 WILL NOT BE ABLE TO RECEIVE OR TRANSMIT DATA WHILE POWERDN IS ASSERTED.
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Data subject to change.
Copyright � 1996 Hewlett-Packard Co.
Printed in U.S.A. 5965-5150E (11/96)
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